1. Field of the Invention
The present invention relates to a synchronism detector circuit and more particularly to a synchronism detector circuit for deciding about states of synchronism between two a.c. voltages, from, for example, an uninterruptible power system (hereinafter to be referred to as CVCF) and the commercial power source.
2. Description of the Prior Art
As a synchronism detector circuit of this kind, the one as shown in FIG. 1 has so far been proposed. Referring to the drawing, numeral reference 1 denotes an inverter used as a CVCF, 2 denotes a commercial power source, and 3 denotes a differential amplifier for amplifying voltage difference between the inverter 1 and the commercial power source 2, the differential amplifier constituted of resistors 4a, 4b, 4c and an operational amplifier 5. Numeral references 6a, 6b denote comparators for comparing a standard signal Vf which provides a detection level with the signal output from the differential amplifier 3 to these comparators 6a and 6b, and 7 denotes an AND circuit for making AND operation for the output signals from the comparators 6a and 6b.
Operation of the circuit in FIG. 1 will be described below. The voltages from the inverter 1 and the commercial power source 2 both having a sinusoidal waveform are input to the differential amplifier 3 for detection of the voltage difference therebetween. When the inverter 1 and the commercial power source 2 are in synchronism, the voltages of the same are equal in amplitude and are in phase. Hence, the level of the output signal from the differential amplifier 3 becomes approximately 0 volt. When, on the other hand, the inverter 1 and the commercial power source 2 are not in synchronism, the output signal from the differential amplifier 3 does not become 0 volt, but becomes .+-. several volts. Such an output signal from the differential amplifier 3 and the reference signal Vf, which is for providing a detection allowance, are compared in the comparators 6a, 6b. When the former is larger than Vf, or smaller than Vf, the output of the comparator 6a or 6b becomes L0, and therefore, the output of the AND circuit 7 becomes L0. The L0 state of the output of the AND circuit indicates that the inverter 1 and the commercial power source 2 are in asynchronism.
If a case of switching from the commercial power source to the CVCF is considered, the voltage of the CVCF should be leading by some degrees, in general, because the power source impedance of the CVCF is larger than that of the commercial power source. Therefore, even in such a condition, the state of synchronism should be decided to be "in synchronism" by the detector circuit. However, the prior art synchronism detector circuit had a disadvantage, because of its structure as described above, that it was unable to independently provide both the voltages with different synchronism detection allowances.